The present invention relates to power factor correction circuits, that is, circuits for reducing the distortion and harmonics generated in a power line feeding a power supply, and in particular a switched mode power supply to make the circuit, including the attached load, appear to be a substantially resistive load. More specifically, the present application relates to a control circuit for use in digital control of a bridgeless power factor correction (PFC) circuit. The aim of power factor correction circuits is to ensure that the AC voltage and current are substantially in phase which improves efficiency and at the same time eliminates the generation of harmful harmonics.
In a conventional boost power factor correction circuit such as that illustrated in FIG. 1, it is common to use a rectifying bridge as illustrated. The rectified AC is provided to the boost inductor L1. A PFC switch Q1 is coupled in series with the inductor and across the output of the bridge rectifier after the inductor. The boost diode BD is coupled in series with the inductor L1 and the output capacitor COUT is coupled as shown at the output of the boost converter circuit in known fashion. The voltage across the capacitor COUT comprises the DC bus voltage which is provided to a load which might comprise, for example a DC to AC inverter driving a three phase motor load ML, for example.
The boost converter circuit is typically controlled via a control circuit in the manner illustrated in FIG. 2. The output of the DC bus Vdc is provided to an A to D converter 10 which has as inputs the DC bus voltage Vdc, the current IIN in the inductor L1 as sensed by a resistor R1 or by other sensing means, as well as the rectified AC input voltage VIN. The A to D converter produces three outputs comprising digital implementations of the DC bus voltage, VdcFdb, the input voltage V_IN and the inductor current I_IN.
A ramp generator 20 receives a DC target voltage VdcTgt. The output of the ramp generator is provided to a difference circuit 22 in which the DC bus voltage is subtracted from the ramp voltage. This is fed to a voltage regulator which may comprise a PI controller 24. The output of the PI controller 24 is fed to a multiplier circuit 26 wherein the voltage output from the voltage regulator (PI controller) and the input voltage V_IN are multiplied. This results in a reference PFC signal IREF_PFC 28, from which the inductor current is subtracted in a difference stage 30. The output of this difference stage 30 is fed to a current regulator 32 comprising a PI controller. The output of the controller 32 is fed to a comparator 34 wherein the PWM signal is generated by comparing an oscillator signal typically a ramp or sawtooth signal 36 generated by an oscillator with the output of the controller 32. This controls the duty cycle of the PWM signal provided to control the switch Q1 and thereby control the power factor correction.
The traditional boost power factor correction circuit, utilizing the bridge rectifier, however, has some drawbacks and thus it is often advantageous to utilized a bridgeless power factor correction circuit such as that illustrated in FIG. 3, for example. It is noted that in the bridgeless PFC only two devices are in series in each current flowing path, thus reducing total forward voltage drop, conduction losses and improving efficiency of the circuit. In addition, since two IGBT's Q1, Q2 are utilized, the thermal stress on each is reduced by 50%. These features have lead to an increased use of bridgeless PFC circuits in motor drive applications, such as air conditioners for example.
The control of bridgeless PFC circuits, however, has not developed quickly. In fact, the utilization of digital control circuits for controlling bridgeless PFC circuits has been unknown until now. One of the challenges to the control of the bridgeless PFC circuits is how to sense the input AC line voltage to provide a sinusoidal reference to shape the PCF current. The PFC control circuit needs a rectified half-sinusoidal AC voltage signal which refers to the negative DC bus voltage as ground. In the conventional PFC circuit, the rectified half sinusoidal AC voltage is available as a result of the use of the bridge rectifier. Naturally, this half sinusoidal AC voltage is not available in the absence of the bridge rectifier.
While some solutions have been proposed to solve this problem, such as the use of an additional isolation transformer and an additional diode bridge rectifier, or the use of an opto-coupler and an additional processing circuit to obtain a zero crossing point of the input AC line voltage, these solutions add significantly to cost and the complexity of the circuit.
An aim of the present invention is to provide a digital control circuit for use with a bridgeless PFC circuits that avoids the problems noted above.